COA

Chapter 1: Introduction

• 2082 Bhadra (Q1) — Compare between computer architecture and organization. Explain the types of bus used in computer organization. [3+3]
• 2081 Baishakh (Q10) — Discuss about loosely-coupled and tightly-coupled architecture. [4]
• 2081 Bhadra (Q1) — Distinguish between computer organization and architecture. Explain instruction cycle state diagram with interrupt handling. [3+3]
• 2080 Baishakh (Q1) — Define structure and function of a computer system. Draw instruction cycle state diagram with interrupt. [4+2]
• 2080 Bhadra (Q1) — Discuss the usage of a multiple hierarchical bus architecture over a single bus system. Design a 1-bit ALU that can perform addition, AND, OR, and XOR operations. Explain the different types of instruction formats. [4+4]
• 2078 Bhadra (Q4) — Explain the organization structure of a microprogram control unit and the generation of microprogram control signals. [5]
• 2078 Bhadra (Q3) — Explain the components of CPU. Compare between RISC and CISC architecture. [2+5]
• 2076 Chaitra (Q1) — Draw the instruction cycle state diagram with example. [6]
• 2075 Ashwin (Q3) — Differentiate between RISC and CISC architecture. [6]
• 2075 Chaitra (Q1) — Define computer architecture. Discuss the limitations of using a single bus system to connect different devices. What does the width of address bus represent in a system? [2+2+2]
• 2074 Chaitra (Q1) — Draw instruction cycle state diagram with interrupt and explain. [6]
• 2073 Shrawan (Q10) — Why is an input-output processor needed in an input-output organization? How does a computer know which device issued the interrupt if multiple devices request service at the same time? [5+5]
• 2073 Shrawan (Q6) — "RISC has the ability to use efficient instruction pipeline." Justify the statement. [3]
• 2073 Shrawan (Q5) — Explain in detail how arithmetic pipeline increases system performance. [7]
• 2068 Chaitra (Q9) — Why is an input-output processor needed in an input-output organization? Explain with block diagram. [10]
• Model Question (Q1) — Compare computer architecture and computer organization. Explain CPI, MIPS rate, MFLOPS rate, and Amdahl's law.

Chapter 2: Central Processing Unit (CPU)

• 2082 Baishakh (Q3) — Explain logical and bit manipulation instructions with example. Describe displacement addressing mode with example. [4+4]
• 2082 Baishakh (Q2) — Write code to evaluate Y=((A+B)*(C-D))/E in three-address, two-address, one-address, and zero-address instruction format. [8]
• 2082 Bhadra (Q3) — Explain instruction format with example. Write code to evaluate the given expression in three-address, two-address, one-address, and zero-address instruction format. [2+8]
• 2082 Bhadra (Q2) — Discuss data manipulation instructions with example. Differentiate between register direct and register indirect addressing modes. [5+5]
• 2081 Baishakh (Q3) — Write down the different types of addressing modes and explain each with advantages and disadvantages. [8]
• 2081 Baishakh (Q2) — Write program for N=((P-Q*R)/S)+((T/U)+V*W) using three-address, two-address, one-address, and zero-address instruction format. Consider P, Q, R, S, T, U, V, W as memory operands. [8]
• 2081 Bhadra (Q3) — Explain data transfer instructions with example. Differentiate between immediate and direct addressing modes. [4+4]
• 2081 Bhadra (Q2) — Write code to evaluate the given expression in three-address, two-address, one-address, and zero-address instruction format. [8]
• 2080 Baishakh (Q3) — What are the different types of addressing modes? Compare them with advantages and disadvantages. [2+6]
• 2080 Baishakh (Q2) — Write code to evaluate the given expression in three-address, two-address, one-address, and zero-address instruction formats. [8]
• 2080 Bhadra (Q4) — Explain address sequencing with the help of a block diagram. Describe micro-instruction format in detail. Show that the speedup factor of a pipelined processor is equal to the number of stages in a pipeline. Explain the different types of conflicts seen in a pipeline. [5+3] [4+6]
• 2080 Bhadra (Q3) — What is addressing mode? Explain the different types of addressing modes with suitable example. [2+6]
• 2078 Bhadra (Q2) — Explain different types of data manipulation instructions with example. [8]
• 2076 Chaitra (Q3) — Define addressing modes. Mention the different types of addressing modes and compare between them. [2+6]
• 2076 Chaitra (Q2) — Write code to evaluate (A - B/C) * [D + (E*G)] in three-address, two-address, one-address, and zero-address instruction formats. [8]
• 2075 Ashwin (Q2) — Write codes for the given operation using zero-, one-, two-, and three-address instruction format. [8]
• 2075 Chaitra (Q1) — Write code for Y=(A+B)/C + D/(E*F) using three-address, two-address, one-address, and zero-address instruction format. [8]
• 2074 Chaitra (Q2) — Write down the need for addressing modes. Explain the various addressing modes with example. [8]
• 2073 Shrawan (Q3) — The following instructions are given: LDA 2000H, MVI B,32H, STAX D, MOV A, B. Which addressing modes are used in the above instructions? Explain briefly. [10]
• 2073 Shrawan (Q2) — Write code for Y=A*(B+D/C)+(G*E)/F using three-address, two-address, one-address, and zero-address instruction format. [8]
• 2068 Chaitra (Q4) — Explain various fields in micro-instruction format with neat block diagram. Describe how the address of control memory is selected. [3+7]
• 2068 Chaitra (Q3) — Define addressing mode. Explain different types of addressing modes with example. [10]
• 2068 Chaitra (Q2) — What are the most common fields in an instruction? How can you perform X=(E+F)*(G+H) using zero-, one-, two-, and three-address instruction format, assuming E, F, G, H, X are memory addresses? [8]
• 2068 Baishakh (Q2) — What are the different types of addressing modes? Compare each with algorithm as well as advantages and disadvantages. [8]
• Model Question (Q2) — How is effective address calculated in different types of addressing modes? Explain with an example.

Chapter 3: Control Unit

• 2082 Baishakh (Q4) — Explain the basic hardwired control unit components and mention the major steps in designing a hardwired control unit. [4+6]
• 2082 Bhadra (Q4) — Compare main memory and control memory. Explain microprogram sequencer for control memory with block diagram. [4+6]
• 2081 Baishakh (Q4) — Explain the micro-instruction format. Differentiate between symbolic and binary micro-instruction. [4+4]
• 2081 Bhadra (Q4) — Write a microprogram for the fetch cycle and addition cycle. Explain the micro-instruction format with example. [5+5]
• 2080 Baishakh (Q1) — Differentiate between hardwired and microprogrammed control unit. Explain with block diagram of microprogrammed control unit. [5+5]
• 2076 Chaitra (Q4) — How is the address of micro-instruction generated by the next address generator in control unit? Explain with suitable diagram. [8]
• 2075 Ashwin (Q4) — Draw the diagram of microprogrammed sequencer for a control memory and explain it. [10]
• 2075 Chaitra (Q4) — Differentiate hardwired and microprogrammed control unit. Draw and explain block diagram of microprogrammed sequencer for control memory. [10]
• 2074 Chaitra (Q3) — Compare and contrast between hardwired and microprogrammed control unit. Explain the microprogram sequencer used in microprogrammed control unit. [4+6]
• 2073 Shrawan (Q4) — Explain micro-instruction format used in microprogramming control unit and write microprogram for fetch cycle. [6+4]
• 2068 Baishakh (Q4) — What are the three types of control signals? Explain the key steps of hardware implementation of control unit. [3+7]
• Model Question (Q3) — Differentiate between hardwired control unit and microprogrammed control unit. Describe address sequencing with the help of block diagram.

Chapter 4: Memory System

• 2082 Baishakh (Q8) — Why is memory hierarchy required in a computer system? Explain the least recently used (LRU) replacement algorithm with example. [3+5]
• 2082 Bhadra (Q8) — What do you mean by mapping function? Why is replacement policy used in fully associative mapping and set associative mapping? Explain with example. [2+6]
• 2081 Baishakh (Q8) — Explain the characteristics of a memory system. Differentiate between direct mapping and set associative mapping. [3+7]
• 2081 Bhadra (Q8) — Describe cache memory principles. Differentiate between direct mapping and set associative mapping. [3+5]
• 2080 Baishakh (Q8) — What is set associative mapping? Explain how it combines the features of direct and associative mapping techniques. Explain different replacement algorithms used in cache memory. [2+3+3]
• 2080 Bhadra (Q8) — Explain direct cache mapping technique with example. Explain different write policy techniques in cache memory. [7+3]
• 2078 Bhadra (Q8) — Explain Least Recently Used (LRU) replacement algorithm in case of hit and miss with suitable example. [8]
• 2076 Chaitra (Q7) — Define cache mapping techniques. Explain direct mapping technique with suitable diagram. Why is replacement algorithm necessary in associative mapping? Justify. [2+4+4]
• 2075 Ashwin (Q8) — Explain the various elements of cache design and also explain the mapping techniques used in cache with example. [4+6]
• 2075 Chaitra (Q8) — Write characteristics of memory system. Suppose main memory has 64 blocks and cache memory has 8 blocks. Show how direct mapping is performed when 10 blocks of main memory are used. [4+6]
• 2074 Chaitra (Q8) — Write down the characteristics of memory system. Suppose main memory has 32 blocks and cache memory has 8 blocks. Show how direct mapping is performed when 12 blocks of main memory are used. [4+6]
• 2073 Shrawan (Q9) — Describe how set associative mapping combines the features of direct and associative mapping technique. Explain different write policy techniques in cache memory. [5+3]
• 2068 Chaitra (Q8) — Explain cache read operation. What are the demerits of direct mapping technique used in cache design, and describe in detail any one mapping technique that solves these problems. [8]
• 2068 Baishakh (Q6) — Explain the key characteristics of computer memory systems. [8]
• 2068 Baishakh (Q5) — What do you mean by mapping process? Differentiate between direct, associative, and set associative mapping. [2+8]
• Model Question (Q4) — Explain associative cache mapping technique with suitable example. Describe the Least Recently Used (LRU) replacement algorithm with case example of miss and hit.

Chapter 5: Computer Arithmetic

• 2082 Baishakh (Q7) — Explain the floating-point multiplication and division process with example. [3+3]
• 2082 Baishakh (Q6) — Draw a flowchart for non-restoring division algorithm and describe the steps. Divide 12/5 using non-restoring division algorithm. [5+5]
• 2082 Bhadra (Q7) — Draw the flowchart of floating-point division. [5]
• 2082 Bhadra (Q6) — Divide 11/3 using non-restoring division algorithm. [6]
• 2081 Baishakh (Q7) — Multiply 10 x (-7) using Booth's multiplication algorithm. [6]
• 2081 Baishakh (Q5) — Construct time-space diagram for four instructions with four-stage pipeline and show how pipelining reduces execution time. Explain arithmetic pipeline for solving floating-point addition/subtraction. [5+5]
• 2081 Bhadra (Q7) — Explain the floating-point addition and subtraction process with example. [3+3]
• 2081 Bhadra (Q6) — Draw a flowchart for Booth's multiplication algorithm for signed multiplication. Multiply -6 x 7 using Booth's multiplication algorithm. [5+5]
• 2080 Baishakh (Q7) — Multiply -6 x 7 using Booth's multiplication algorithm. [6]
• 2080 Baishakh (Q5) — How can we prove that pipelining improves the performance of a computer? Explain the operation of instruction pipeline for processing four-segment instruction cycle with the help of space-time diagram. Explain non-restoring division algorithm with flowchart and divide 12/5 using the same algorithm. [4+6] [5+5]
• 2080 Bhadra (Q7) — Compare restoring division algorithm with non-restoring division algorithm. [6]
• 2080 Bhadra (Q6) — Explain Booth's algorithm. Multiply (9 x -4) using Booth's multiplication algorithm. [4+4]
• 2078 Bhadra (Q7) — Explain the floating-point addition and subtraction process using flowchart. [3+3]
• 2078 Bhadra (Q6) — Explain the non-restoring division algorithm for division. Divide 10/5 using non-restoring division. [5+5]
• 2076 Chaitra (Q6) — Explain Booth's algorithm for multiplication. Multiply 10 x (-5) using Booth's algorithm. [8]
• 2075 Ashwin (Q7) — Differentiate between restoring and non-restoring division. [6]
• 2075 Ashwin (Q6) — Explain Booth's multiplication algorithm for signed 2's complement numbers in detail with a suitable example and hardware requirement diagram. [10]
• 2075 Chaitra (Q7) — Multiply -6 x -11 using Booth's multiplication. [6]
• 2075 Chaitra (Q6) — Write an algorithm for non-restoring division. Perform 10/3 using restoring division algorithm. [3+7]
• 2075 Chaitra (Q2) — Design a 2-bit ALU that can perform subtraction, AND, OR, and XOR. [8]
• 2074 Chaitra (Q7) — Explain the process of floating-point number addition and subtraction with flowchart and example. [10]
• 2074 Chaitra (Q6) — Perform multiplication -7 x 3 using Booth algorithm. [6]
• 2073 Shrawan (Q8) — Explain floating-point addition and subtraction algorithm with example. [6]
• 2073 Shrawan (Q7) — Explain signed binary division algorithm. Use the non-restoring division algorithm to divide 15 by 4. [8]
• 2068 Chaitra (Q7) — Explain floating-point division algorithm. [6]
• 2068 Chaitra (Q6) — Explain Booth algorithm. Use the Booth algorithm to multiply 23 (multiplicand) by -21 (multiplier), where each number is represented using 6 bits. [8]
• 2068 Baishakh (Q3) — Differentiate between restoring division and non-restoring division with example. [8]
• Model Question (Q5) — Write down the flowchart of Booth's multiplication algorithm. Multiply 7 x -5 = -35 using Booth's multiplication algorithm.

Chapter 6: Pipelining and Vector Processing

• 2082 Baishakh (Q5) — Discuss pipeline conflicts with example. Describe 4-stage instruction pipeline with diagram. [4+6]
• 2082 Bhadra (Q5) — How can parallel processing be achieved in instruction pipeline? Explain the four-segment pipeline having six tasks with time-space diagram. [4+6]
• 2081 Bhadra (Q5) — What is pipelining? Describe four-stage instruction pipeline. Explain Flynn's classification of computer systems. [1+4+4]
• 2078 Bhadra (Q5) — What is meant by hazard in pipelining? Explain with example data and control hazards in pipeline conflict. [4+6]
• 2076 Chaitra (Q5) — Explain four-stage instruction pipeline and draw a time-space diagram for four segments having six tasks. [10]
• 2075 Ashwin (Q5) — Explain six-stage instruction pipeline with example. [10]
• 2075 Chaitra (Q5) — Derive expression showing speedup ratio equals number of segments in pipeline. Discuss in detail the data dependency problem that arises in pipelining along with its solution. [3+5]
• 2074 Chaitra (Q5) — What is pipeline? How is the performance of computer increased using pipelining? Explain with example. [2+6]
• 2068 Chaitra (Q5) — What are the hazards in instruction pipelining? How can they be resolved? Explain. [10]
• Model Question (Q6) — Formulate 4-segment instruction pipeline with branching and interrupts.

Chapter 7: Input/Output

• 2082 Baishakh (Q9) — Compare and contrast DMA and I/O processor. Explain the communication between CPU and IOP communication channel with necessary block diagram. [5+5]
• 2082 Bhadra (Q9) — Explain DMA controller with block diagram. Compare programmed I/O with interrupt-driven I/O. [6+4]
• 2081 Baishakh (Q9) — Why is IOP used in input-output organization? With the help of a neat diagram, explain how DMA technique is used to transfer data in a computer system. [3+7]
• 2081 Bhadra (Q10) — Briefly discuss inter-processor communication and synchronization. [5]
• 2081 Bhadra (Q9) — Compare and contrast programmed I/O and interrupt-driven I/O. Explain the CPU and IOP communication channel using diagram. [5+5]
• 2080 Baishakh (Q9) — Explain CPU-IOP communication with diagram. Explain DMA controller with suitable block diagram. [5+5]
• 2080 Bhadra (Q9) — Explain three I/O techniques for input of a block of data. Show the role of I/O processor to assist the operation of the CPU. [6+4]
• 2078 Bhadra (Q9) — Differentiate between isolated and memory-mapped input-output. Explain DMA transfer in a computer system with block diagram. [4+6]
• 2076 Chaitra (Q9) — Compare programmed I/O, interrupt-driven I/O, and direct memory access. Why is data communication processor required in an I/O organization? [8+2]
• 2075 Ashwin (Q9) — Why is I/O processor needed in I/O organization? Explain CPU-IOP communication with diagram. [3+7]
• 2075 Chaitra (Q10) — Explain inter-processor synchronization with example. [4]
• 2074 Chaitra (Q9) — Explain I/O interface. Compare programmed I/O, interrupt-driven I/O, and direct memory access (DMA). [2+8]
• 2068 Baishakh (Q8) — Compare programmed I/O, interrupt-driven I/O, and direct memory access (DMA). What are the steps to configure a plug-and-play device? Explain. [8] [6]
• 2068 Baishakh (Q7) — Explain input/output interface with example. [6]
• Model Question (Q7) — Compare Programmed I/O, Interrupt-Driven I/O, and Direct Memory Access (DMA).

Chapter 8: Multiprocessor System

• 2082 Baishakh (Q10) — Briefly discuss 8x8 omega switching network with example. [4]
• 2082 Baishakh (Q1) — Explain with example the computer's interconnection structure. [6]
• 2082 Bhadra (Q10) — Compare and contrast the interconnection structures used in multiprocessing system. [5]
• 2080 Baishakh (Q10) — Explain the crossbar switch interconnection structure with block diagram. [4]
• 2080 Bhadra (Q10) — List out the characteristics of a multiprocessor. [4]
• 2078 Bhadra (Q10) — Compare and contrast the interconnection structures used in multiprocessor. [4]
• 2076 Chaitra (Q10) — Discuss hypercube interconnection network with example. [7]
• 2075 Ashwin (Q10) — Write down the characteristics of multiprocessors. [4]
• 2075 Ashwin (Q1) — Explain the interconnection structures of computer. [6]
• 2074 Chaitra (Q10) — Explain various configurations of OS in multiprocessor. [4]
• 2068 Chaitra (Q10) — Define multiprocessor and its characteristics. [4]
• Model Question (Q8) — Explain how multicore processors improve hardware performance with respect to parallelism and power consumption.

No matching questions were found in the provided papers for some new-syllabus topics such as MFLOPS, Berkeley RISC, microoperations, reverse polish notation, shift, status bit, microinstructions, SODIMM, magnetic disk, magnetic tape, integer representation, sign-magnitude, supercomputers, I/O modules, I/O commands, I/O channels, hypercube, and interprocessor arbitration.